11.1 Laboratory communications: lab2 - echo test using spi

Laboratory communications: lab2 - echo test using spi

Introduction

The MSP430 contains built-in features for both parallel and serial data communication. This chapter describes the operation of these peripherals, and discusses the protocols, data formats and specific techniques for each type of data communication.

The communication modules available for the MSP430 family of microcontrollers are USART (Universal Synchronous/Asynchronous Receiver/Transmitter), USCI (Universal Serial Communication Interface) and USI (Universal Serial Interface). These provide asynchronous data transmission between the MSP430 and other peripheral devices when configured in UART mode. They also support data transmission synchronized to a clock signal through a serial I/O port in Serial Peripheral Interface (SPI) and Inter Integrated Circuit (I2C) modes.

Overview

This laboratory explores the USCI and USI communication interfaces in SPI mode. The MSP430 devices included on the Experimenter’s board will exchange messages between themselves, one being the MSP430FG4618 (master) that will control operation of the other MSP430F2013 device (slave). The master, by reading the current state of the slave, will drive the slave to the new desired state, controlling its activity. In this particular case, switching the state of LED3 will be implemented.

Resources

This laboratory uses the USCI module of the MSP430FG4618 device and the USI module included on the MSP430F2013. Both units operate in SPI mode.

The Basic Timer1 of the master device is programmed to switch the status of the slave device once every 2 seconds.

The slave is notified of the arrival of information through the counting end interrupt of the USI module.

The resources used are:

- USCI module;

- USI module;

- Basic Timer1;

- Interrupts;

- I/O ports.

Software application organization

The software architecture for this laboratory is shown in Figure 1.

The master unit is composed of two software modules ( Lab2_Comm_1.c ):

- The "Main master task" module contains the operation algorithm of master unit;

- The "ISR Basic Timer" module wakes the "Main master task" once every 2 seconds.

The slave unit is also composed of two modules ( Lab2_Comm_2.c ):

- The "Main slave task" module contains the operation algorithm of the slave unit;

- The "USI ISR" module reads the data received, prepares the USI module for new reception and wakes the "Main slave task" to execute the algorithm associated with the reception of the new command.

Software architecture

System configuration

Usci_b (master) control registers configuration

The SPI connection will operate in the following mode:

- Clock phase ->Data value is updated on the first UCLK edge and captured on the following edge;

- Clock polarity ->the inactive state is low;

- MSB first;

- 8-bit data;

- Master mode;