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Cross-section of a n-channel JFET in the "ON" state.
Cross-section of a p-channel JFET in the "ON" state.

Mosfet fundamentals

The metal oxide semiconductor field effect transistor (MOSFET) utilizes an oxide layer (typically SiO 2 ) to isolate the gate from the source and drain. The thin layer of oxide prevents flow of current to the gate, but enables an electric field to be applied to the channel which regulates the flow of charge carriers through the channel.MOSFETs unlike JFETs can operate in depletion or enhancement mode characterized by their ON or OFF state at zero gate-source voltage, V GS.

For depletion mode MOSFETs the device is “ON” when the V GS is zero as a result of the devices structure and doping scheme. The n-channel depletion mode MOSFET consists of heavily n-doped source and drain terminals on top of a p-doped substrate. Underneath an insulating oxide layer there is a thin layer of n-type silicon which allows charge carriers to flow in the absence of a gate voltage. When a negative voltage is applied to the gate a depletion region forms inside the channel, as seen in [link] . If the gate voltage is sufficient the depletion region pinches off the flow of electrons.

Cross-section of a n-channel depletion mode MOSFET when a negative gate voltage is applied with the resultant depletion layer.

For enhancement mode MOSFETs the ON state is attained by applying a gate voltage in the direction of the drain voltage; a positive voltage for n-channel enhancement MOSFETs, and a negative voltage for p-channel enhancement MOSFETs. The term “enhancement” is derived from the increase in conductivity seen by applying a gate voltage. This increase in conductivity is enabled by an inversion layer induced by the applied electric field at the gate as shown in [link] for n-channel enhancement mode MOSFETs and [link] for p-channel enhancement mode MOSFETs respectively.

A depiction of the induced inversion layer with n-type charge carriers in a n-channel enhancement mode MOSFET.
A depiction of the induced inversion layer with p-type charge carriers in a p-channel enhancement mode MOSFET.

The thickness of this inversion layer is controlled by the magnitude of the gate voltage. The minimum voltage required to form the inversion layer is called the gate-to-source threshold voltage, V T . In the case of n-channel enhancement mode MOSFETs, the “ON” state is reached when V GS >V T and a positive drain-source voltage, V DS , is applied. If the V GS is too low, then increasing the V DS further results only in increasing the depletion region around the drain. The p-channel enhancement mode MOSFETs operate similarly except that the voltages are reversed. Specifically, the “ON” state occurs when V GS <V T and a negative drain-source voltage is applied.

Measurement of key fet parameters

In both an academic and industrial setting characterization of FETs is beneficial for determining device performance. Identifying the quality and type of FET can easily be addressed by measuring the transport characteristics under different experimental conditions utilizing a semiconductor characterization system (SCS). By analyzing the V-I characteristics through what are called voltage sweeps, the following key device parameters can be determined:

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Source:  OpenStax, Physical methods in chemistry and nano science. OpenStax CNX. May 05, 2015 Download for free at http://legacy.cnx.org/content/col10699/1.21
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