Laboratory flash memory: lab1 - flash memory programming with the

Laboratory flash memory: lab1 - flash memory programming with the cpu executing the code from flash memory

Introduction

The TI MSP430 has an internal flash memory that can be used for data storage. Two different methods of writing to the flash memory are studied in this laboratory. The first method requires the CPU execution of the code resident in flash memory. The consequences of this procedure are discussed. In the second part of the laboratory, the flash write and erase operations are conducted with the CPU executing the code resident in RAM. The important details are highlighted.

Overview

This laboratory programs the internal flash memory with the CPU executing the code resident in flash memory. It requires to configure: - Flash memory controller; - Segment erase routine; and the - Flash write routine. The execution time of the different operations can be obtained with an oscilloscope connected on pin 2 of the Header 4 or analyzing the state of the LED (digital output P2.1).

Resources

This laboratory uses the flash memory controller. The operation of this device is monitored using a digital output port (P2.1).

The project must be compiled using the files ( Lab1_Flash.c )and the command file lnk_msp430fg4618.cmd.

The code is resident in the flash memory, so whenever a flash write or erase operation occurs, the CPU access to this memory is automatically inhibited.

Software application organization

The software begins by disabling the Watchdog Timer. Then, port P2.1 is set as an output with a logic low level.

The flash memory controller is configured with the clock MCLK divided by 3. Thus the fFTG operating frequency lies within the specified limits of 257 kHz to 476 kHz.

A set of routines are provided to erase, write and copy the contents of a segment. The main tasks related to the flash memory handling are presented using this set of routines.

The information Segments A and B are erased first. Then, bytes are written to SegmentA and words are written to SegmentB. The contents of the information memory SegmentA are copied to the information SegmentB, overwriting the previous contents.

System configuration

Flash memory controller configuration

Configure the register FCTL2 to use clock MCLK divided by 3. Do not forget to enter the password to access the register.

FCTL2 = FWKEY | FSSEL0 | FN1; // MCLK/3 for Flash Timing Generator

Segment erase routine

Configure the registers FCTL1 and FCTL3 in order to initiate the flash segment erase process by writing an address belonging to the segment to be erased. Be sure to include the password to access the register.

Block flash write and erase operations are carried out after erasing the segment:

Flash write routine

Configure the registers in order to start writing to the flash memory. Be sure to include the password to access the register.

Configure flash block write and erase operations and disable the write bit:

Analysis of operation

Execution time for the information segments erase operation

Put the cursor at line of code 124, located just after the second port P2.1 switching state. Execute the software until the cursor position is reached. The erase operation timing can be seen on an oscilloscope with the probe connected to pin 2 of the Header 4.

Bytes write in the information memory a

The routine write_char_flash allows writing a byte to flash memory. It receives the memory address where the byte should be stored.

Open the memory window, and add the address of the information memory A. The content of this address becomes visible after ordering its rendering . As we are writing a byte to flash, we must change the presentation of the memory contents. Choose the option Column Size 1 , from the context menu of the memory window, through the option Format .

Now, during the execution of the for loop, the flash contents is written sequentially.

Bytes written in the information b memory

This routine is similar to the previous one. Note that now the flash write address is increased by two because a word occupies two bytes of memory.

The information is more readily observed when the memory contents display mode is restored to its initial state. Reset the default conditions in the option Format of the context menu.

Copy the contents of the information a memory to information b memory

The output port P2.1 is enabled before the copy process begins. The copy routine receives the start address of the source information segment and the start address of the destination information segment. The information is then successively read and written from one segment to another.

Port P2.1 is disabled at the end of the copy process. Thus, the task execution time can be measured using an oscilloscope.

This example and many others are available on the MSP430 Teaching ROM.

Request this ROM, and our other Teaching Materials here (External Link)