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Using the DMA controller included in the MSP-EXP430FG4618 Development Tool analysed the data transfer between two regions of memory.

Laboratory dma: lab1 - data memory transfer triggered by software

Introduction

This laboratory gives an example of the use of the DMA peripheral available in the MSP-EXP430FG4618 Development Tool. It requires the configuration of the DMA Source and Destination Addresses Registers, DMA Size Address Register; DMA Control Registers and DMA Channel 0 Control Register in order to transfer data between two regions of memory.

Overview

During this laboratory ( Lab1_DMA.c ), the data transfer between two regions of memory is analyzed. The order of transfer is controlled by software.

Resources

The following resource is used in this laboratory:

- DMA controller.

Software application organization

The software begins by disabling the watchdog timer. Port P2.1 is set as an output with a logic low level.

The memory addresses of the data vectors are passed to the source data address DMA0SA and destination address DMA0DA registers.

The number of words to be transferred is loaded in the DMA0SZ (size) register.

The DMA channel 0 is configured so that the data transfer trigger is controlled by software, in order that after each transfer, the source and destination addresses are correctly incremented.

The application enters an infinite loop, where port P2.1 state is switched just before initiating the data transfer.

System configuration

Dma channel configuration:

The source address and destination address of the data must be loaded into their respective registers:

DMA0SA = (void (*)( ))&tab_1; // Start block addressDMA0DA = (void (*)( ))&tab_2; // Destination block address

To move a total of 32 words, what is the value to write to the data size register?

DMA0SZ = 0x0020; // Block size

The DMA channel must be configured to transfer the word under software control. The source and destination addresses should be incremented immediately after each of the transfers.

DMA0CTL=DMADT_0 | DMASRCINCR_3 | DMADSTINCR_3 | DMAEN; // Single transfer,// DMA source and destination addresses increment, // Enable DMA0

Analysis of operation

In the Memory window, the addresses of data vector Tab_1 and Tab_2 addresses are displayed. The contents of these blocks must be identified in memory.

Add a breakpoint at line of code that performs the switching of port P2.1 state.

Execute the application, and whenever the breakpoint is reached, the execution of the application will be suspended. Observe the data being gradually transferred from source to destination.

The data transfer is suspended once the 32 elements of the source data vector have been transferred.

This example and many others are available on the MSP430 Teaching ROM.

Request this ROM, and our other Teaching Materials here (External Link)

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Source:  OpenStax, Teaching and classroom laboratories based on the “ez430” and "experimenter's board" msp430 microcontroller platforms and code composer essentials. OpenStax CNX. May 19, 2009 Download for free at http://cnx.org/content/col10706/1.3
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