Interrupts  (Page 4/3)

An interrupt is an event in hardware that triggers the processor to jump from its current program counter to a specific point in the code. Interrupts are designed to be special events whose occurrence cannot be predicted precisely (or at all). The MSP has many different kinds of events that can trigger interrupts, and for each one the processor will send the execution to a unique, specific point in memory. Each interrupt is assigned a word long segment at the upper end of memory. This is enough memory for a jump to the location in memory where the interrupt will actually be handled. Interrupts in general can be divided into two kinds- maskable and non-maskable. A maskable interrupt is an interrupt whose trigger event is not always important, so the programmer can decide that the event should not cause the program to jump. A non-maskable interrupt (like the reset button) is so important that it should never be ignored. The processor will always jump to this interrupt when it happens. Often, maskable interrupts are turned off by default to simplify the default behavior of the device. Special control registers allow non-maskable and specific non-maskable interrupts to be turned on. Interrupts generally have a "priority;" when two interrupts happen at the same time, the higher priority interrupt will take precedence over the lower priority one. Thus if a peripheral timer goes off at the same time as the reset button is pushed, the processor will ignore the peripheral timer because the reset is more important (higher priority).

The function that is called or the particular assembly code that is executed when the interrupt happens is called the Interrupt Service Routine (ISR). Other terms of note are: An interrupt flag (IFG) this is the bit that is set that triggers the interrupt, leaving the interrupt resets this flag to the normal state. An interrupt enable (IE) is the control bit that tells the processor that a particular maskable interrupt should or should not be ignored. There is usually one such bit per interrupt, and they are often found together in a register with other interrupt enable bits. The most important interrupt on MSP430 is the reset interrupt. When the processor detects a reset or powers up for the first time, it jumps to the beginning of memory and executes the instructions there. The highest priority interrupt vector begins at the address 0xfffe. The lowest priority interrupt begins at 0xFFE0. The complete set of interrupts is ranked by priority:

• 15 non-maskable: External reset, power up, watchdog timer reset, invalid flash memory activation
• 14 non-maskable: oscillator fault, flash memory access violation, NMI
• 13 maskable: timer B capture compare register 0
• 12 maskable: timer B capture compare registers 1-6, timer B interrupt
• 11 maskable: comparator A interrupt
• 10 maskable: watchdog timer interrupt
• 9 maskable: USART0 receive interrupt, I2C interrupt
• 8 maskable: USART0 transmit interrupt
• 7 maskable: A/D converter interrupt
• 6 maskable: timer A capture compare register 0 interrupt
• 5 maskable: timer A capture compare registers 1-2 interrupt
• 4 maskable: port 1 interrupts
• 3 maskable: USART1 receive interrupt
• 2 maskable: USART1 transmit interrupt
• 1 maskable: port 2 interrupts
• 0 maskable: D/A converter interrupt