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C6x addressing modes.
Syntax Memory address accessed Pointer modification
*R R None
*++R R Preincrement
*--R R Predecrement
*R++ R Postincrement
*R-- R Postdecrement
*+R[disp] R+disp None
*-R[disp] R+disp None
*++R[disp] R+disp Preincrement
*--R[disp] R+disp Predecrement
*R++[disp] R+disp Postincrement
*R--[disp] R+disp Postdecrement

The [disp] specifies the number of elements in word, halfword, or byte, depending on theinstruction type and it can be either 5-bit constant or a register . The increment/decrement of the index registers are also in termsof the number of bytes in word, halfword or byte. The addressing modes with displacements are useful when a blockof memory locations is accessed. Those with automatic increment/decrement are useful when a block is accessedconsecutively to implement a buffer, for example, to store signal samples to implement a digital filter.

(Load from memory): Assume the following values are stored in memory addresses:

Loc 32-bit value 100h fe54 7834h104h 3459 f34dh 108h 2ef5 7ee4h10ch 2345 6789h 110h ffff eeddh114h 3456 787eh 118h 3f4d 7ab3h

Suppose A10 = 0000 0108h . Find the contents of A1 and A10 after executing the each of the following instructions.

  1. LDW .D1 *A10, A1
  2. LDH .D1 *A10, A1
  3. LDB .D1 *A10, A1
  4. LDW .D1 *-A10[1], A1
  5. LDW .D1 *+A10[1], A1
  6. LDW .D1 *+A10[2], A1
  7. LDB .D1 *+A10[2], A1
  8. LDW .D1 *++A10[1], A1
  9. LDW .D1 *--A10[1], A1
  10. LDB .D1 *++A10[1], A1
  11. LDB .D1 *--A10[1], A1
  12. LDW .D1 *A10++[1], A1
  13. LDW .D1 *A10--[1], A1

Storing data to memory

Storing the register contents uses the same addressing modes. The assembly instructions used for storing are STB , STH , and STW .

(Storing to memory): Write assembly instructions to store 32-bit constant 53fe 23e4h to memory address 0000 0123h .

Sometimes, it becomes necessary to access part of the data stored in memory. For example, if you store the 32-bit word 0x11223344 at memory location 0x8000 , the four bytes having addresses location 0x8000 , location 0x8001 , location 0x8002 , and location 0x8003 contain the value 0x11223344 . Then, if I read the byte data at memory location 0x8000 , what would be the byte value to be read?

The answer depends on the endian mode of the memory system. In the little endian mode , the lower memory addresses contain the LSB part of thedata. Thus, the bytes stored in the four byte addresses will be as shown in [link] .

Little endian storage mode.
0x8000 0x44
0x8001 0x33
0x8002 0x22
0x8003 0x11

In the big endian mode , the lower memory addresses contain the MSB part of the data. Thus, we have

Big endian storage mode.
0x8000 0x11
0x8001 0x22
0x8002 0x33
0x8003 0x44

In the C6x CPU, it takes exactly one CPU clock cycle to execute each instruction. However, the instructions such as LDW need to access the slow external memory and the results of the load are not availableimmediately at the end of the execution. This delay of the execution results is called delay slots .

For example, let's consider loading up the content of memory content at address pointed by A10 to A1 and then moving the loaded data to A2 . You might be tempted to write simple 2 line assembly codeas follows:

1 LDW .D1 *A10, A1 2 MV .D1 A1,A2

What is wrong with the above code? The result of the LDW instruction is not available immediately after LDW is executed. As a consequence, the MV instruction does not copy the desired value of A1 to A2 . To prevent this undesirable execution, we need to make the CPU wait until the resultof the LDW instruction is correctly loaded to A1 before executing the MV instruction. For load instructions, we need extra 4 clock cycles until the loadresults are valid. To make the CPU wait for 4 clock cycles, we need to insert 4 NOP (no operations) instructions between LDW and MV . Each NOP instruction makes the CPU idle for one clock cycle. The resulting code will be likethis:

1 LDW .D1 *A10, A1 2 NOP3 NOP 4 NOP5 NOP 6 MV .D1 A1,A2

or simply you can write

1 LDW .D1 *A10, A1 2 NOP 43 MV .D1 A1,A2

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Source:  OpenStax, Dsp lab with ti c6x dsp and c6713 dsk. OpenStax CNX. Feb 18, 2013 Download for free at http://cnx.org/content/col11264/1.6
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