# 9.4 Sspd_chapter 7_part3_electrical properties of mos continued2  (Page 2/2)

Short Circuit Current Gain is derived as:

Where

Therefore

7.3.24

In exactly the same manner short circuit current gain of NMOS is derived and set to unity.

7.3.25

Where

In Eq.7.3.25, ω 0 = 5 ω u therefore, in working range of frequencies, Equation 7.3.25 can be simplified to:

7.3.26.

If Equation 7.3.26 is equated to Unity then its corresponding Unity Gain Frequency is:

7.3.27

From Eq.7.3.27 it is evident that increase in transconductance gives a higher frequency range of opeartaion.

7.3.7. Theoretical Formulation of Output Conductance of (E)NMOS.

Theoretical expression of drain current in saturation region is given by Equation 7.3.16:

As is evident from the above Equation, I ds has no dependence on V ds and I ds -V ds family of curves are perfectly horizontal and parallel to one another. Horizontal I-V curve implies infinite output impedance of the active device. But in practice it is not so. Real MOS devices have slopes in their family of I-V curves and this slope becomes pronounced as we scale the devices for the different generation of Technology. This is known as Channel Length Modulation effect.

In BJT we have Base Width Modulation also known as Early Effect. This Early Effect is the cause of the slope in output family of curves of CB BJT and CE BJT. Due to these slopes we have h ob and h oe parameters in the two circuit configurations. Since Early Effect is more pronounced in CE BJT hence h oe = 1/40kΩ is greater than h ob = 1/2MΩ. Channel Length Modulation is analogous to Early Effect and its degradation of family of output curves of NMOS is clealrly brought out in Figure 7.3.2. The physics of this degradation is that we have assumed that after saturation, I ds (sat) becomes constant at:

7.3.2

In Equation 7.3.2 it is assumed that with increase in V DS , the voltage drop across the conical channel is constant at V DS * and excess voltage drops across the pinched off region. The second assumption is that the resistance of the conical section is constant at :

R 0 /3 where R 0 is the resistance of the parallelopied channel.

This assumption does not remain valid with the scaling of devices. As the the device is scaled, the variation in V ds leads to significant change in the resistance of the conical channel because as pinched off region increases the axial length of the conical channel reduces and hence resistance offered decreases and I DS(sat) increases with the increase in V DS .

Channel Length Modulation is included in the saturated drain current in the following manner:

7.3.28

Where λ = channel length modulation parameter which is dependent on channel length L and its typical values are:

.

Therefore the partial derivative of I ds with respect to V ds with gate voltage constant gives the the reciprocal of the incremental output resistance of (E)NMOS:

7.3.29

The overall dependence of 1/r ds is :

7.3.30.

The incremental model of MOSFET incorporating transconductance and channel length modulation is given in Figure 7.3.1.

7.3.8. Figure of Merit of MOSFET.

The Unity Gain Bandwidth of MOSFET defines the Figure of Merit of MOSFET. Using Equation 7.3.27:

7.3.31

Transconductance is given as:

Or

7.3.23

Where

Gate Capacitance is given as:

Substituting Eq.7.3.23 and 7.3.13 in Eq.7.3.31 we get:

From Equation 7.3.7

Therefore Figure of Merit is the reciprocal of the transit time across the channel.

Larger is the electron mobility, better will be the Figure of Merit. Hence<100>orientation Si Substrate is chosen for fabrication of CMOS circuis. The mobility of electron and hole is always much larger in<100>orientation substrate than that in<111>orientation substrate. In Table 7.3.2 a comparative study of the electron mobility in<111>and<100>substrate is given.

Table 7.3.2. Comparative study of mobilities in<100>and<111>orientation substrate in thin channel and in bulk.

 Bulk mobility<100> 2D channel mobility<100> 2D Channel mobility<111> µ n 1250cm 2 /(V-sec) 650 cm 2 /(V-sec) 500 cm 2 /(V-sec) µ p 480 cm 2 /(V-sec) 240 cm 2 /(V-sec) 216 cm 2 /(V-sec)

For fast CMOS circuits fabrications,<100>Si Substrate is the choice of material in Industries.

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