9.25 Sspd_chapter 7_part 6_basic circuit concepts_concluded

SSPD_Chapter 7_Part 6_Basic Circuit Concepts_concluded

7.6.9. Wiring Capacitances.

We have already discussed area capacitances and its effects on the speed of switching. Here we will discuss the various parasistic capacitances associated with the interconnection wirings. These need to be accounted along with the area capacitances while studying the performance of CMOS circuits. Three main sources of wiring parasitic capacitances are: fringing fields, interlayer capacitances aand peripheral capacitances.

7.6.9.1.Fringing Fields.

In any area parallel-plate capacitance there are transverse field lines as well as fringing field lines which can be significant fraction of the transverse field line as shown in Figure 7.6.9.1. In the standard parallel plate formula (εA/d) which is used for area capacitance calculation we account for transverse field only. To consider the total capacitance we need to calculate the Capacitance due to fringe field.

Where

It is given:

FF is plotted in Figure 7.6.9.2.

From the graph in Figure 7.6.9.2 it is evident that narrower and thicker interconnect segment has a much larger Fringing Field Effect .

Pucknell et.al give the formula for fringing field capacitance for fine line metallization. It is as follows:

Where L=wire length,

t = thickness of the wire,

h = wire to substrate separation.

7.6.9.2. Interlayer capacitance.

In multi-level metallization IC Chip, interlayer capacitance becomes important therefore in area capacitance chart Table 7.6.2. we have metal 2 to metal 1 and metal 2 to polysilicon. This will occur where two level metal paths overlap or cross each other.

7.6.9.3.Inter-wire Capacitance(due to lateral field).

There is inter-wire capacitance between two metal pathways at the same level due to lateral field as shown in Figure 7.6.9.3. Along side Fringe Field Capacitance and Parallel Plate Capacitance is also shown.

7.6.9.4. Overlap Fringe Field Capacitance.

Two level metal pathways may overlap as shown in Figure 7.6.9.4. In this case Overlap Fringe-Field Capacitance is caused.This has to be ascounted for accurate modeling and simulation.

7.6.9.5. Peripheral Capacitance.

In Table 7.6.2 we have a row which gives the diffusion(active)region capacitance. These are the junction capacitance of the junction diode made by source and drain diffusion into the Well or into the substrate.

In Figure 7.6.9.5 we show the cross-section of CMOS structure achieved by N-Well Process.

We have P+ Source and P+Drain diffusion into N-Well to realize PMOS and we have N+Source and N+Drain diffusion into P-Substrate to realize NMOS. This created 12 PN Junction Diodes.