9.24 Sspd_chapter 7_part 6_basic circuit concepts_continued 6

SSPD_Chapter 7_Part 6_Basic Circuit Concepts_continued 6.

7.6.8. Propogation delays.

A typical Electronic System as shown in Figure 7.6.8.1 consists of several modules interconnected through high bit transfer buses. Each module is a PCB which interconnect several ICs through copper tracks etched out on the PCB. Each IC itself has several hundreds of millions of transistors interconnected to achieve a Systen-on-Chip through metal paths or silicide paths.

These metal/silicides interconnects is becoming the biggest bottleneck both cost and performance wise. Scaling of the metal paths pitch in larger and complexICs is leading to long transmission lines with interconnect delay dominating the chip delay as shown in Figure 7.6.8.2.

Metallic/Silicides pathways or interconnects on the IC Chip act as the data bus as well as the instruction bus. As the clock speed goes up, these interconnect face skin effect and eddy current losses. Skin effect leads to excessive resistance and heat dissipation. The oscillating signals on the buses induce stray eddy current in the board’s conducting part leading to heavy eddy current losses. With increase in clock rate, attenuation along the copper buses increases exponentially. At 2GHz clock, there is 50% attenuation and at 10GHz, there is 95% attenuation. At few GHz several resonances occur which cause signal to be reflected from the VIAS.

Apart from this, there is severe cross-talk among the metallic interconnects leading to excessive Bit Error Rate (BER). At 10Gb.p.s. rates, cross-talk blurs the signal after 1 meter of ppropogation down the coper bus.

With the increase in the processing speed, the problem of attenuation and cross-talk is becoming more acute.

7.6.8.1.Comparison between metallic and electro-optical interconnects.

In Figure 7.6.8.3 a comparative study is made between metallic interconnect and electro-optical interconnect in terms of propogation delayencountered.

In Figure 7.6.8.3 we see that the propogation delay is halfed using electro-optical interconnect as opposed to metallic interconnect.

7.6.8.2. Delay through Cascaded Pass Transistors.

A chain of four cascaded pass transistors and its equivalent distributed circuit model is shown in Figure 7.6.8.3. The gates of the pass transistors are held at V _DD so that all the pass transistors are ON.

Consider nodes 1,2 and 3.

At node 2 we have:

But

7.6.8.2

Using Eq 7.6.8.1 and Eq.7.6.8.2

Rearranging the terms of Eq.7.6.8.3

Therefore

Eq.7.6.8.4 has been derived in Pucknell’s book but this equation is not the standard wave equation. Hence it doesnot have a standard solution and is very difficult to understand as to how Pucknell concludes that the propogation delay = t _pd is given as:

In the Book ‘VLSI Design Techniques for Analog&Digital Circuits’ by Randell L.Geiger, Phillip E.Alen and Noel R.Strader, Publisher McGraw Hill Series, 1990, 969 pages,Chapter 7 ‘Basic Digital Building Block’, Section 7.7.1 NMOS Pass Transistors, Page 561, above statement is very clearly inferred by deduction.

The delay for one section is RC.

If second pass transistor is added and only capacitance is considered then delay for two sections will be (R2C);

If second pass transistor is added and second series resistance is considered and capacitance is neglected then delay for two sections will be (2RC);

If while considering two sections 2R and 2C are considered then

Delay is 2R×2C=4RC=2 ² RC.

If N pass transistors are considered then delay = N ² RC.

Hence in a cascade of pass transistors more than 4 NMOS are never used. If a long chain has to be used then it must be segmented at intervals of 4 NMOS by inverters.