8.27 Sspd_chapter 6_part 8_caliberating athena for typical mosfet  (Page 2/4)

Turning to electrical data, the most important device electrical data is a plot of threshold voltage versus gate length for the NMOS devices. Figure 7.40 shows typical plots of threshold voltage versus gate length. In this figure, the RTA anneal temperature and times were varied to show the various profiles that can be expected. A more typical plot is represented by the 1000°C RTA profile, showing a peak value around 1-2 microns with a tail off for longer or shorter gate lengths.

Figure 7.40: A plot of Threshold Voltage vs. Gate Length for NMOS devices(given in next module)

Gate oxide thickness measurements are also required. Be careful here if oxide thickness is measured with capacitance-voltage (C-V) methods, since quantum effects in very thin oxides (less than 5nm) can lead to inaccuracies because the actual location of the peak concentration of the accumulation charge is not at the interface as classic physics predicts but a short distance into the silicon. Use the QUANTUM model in ATLAS to match accumulation capacitance with oxide thickness for very thin oxides.

Other useful electrical input information is data that won’t be used now but later for the calibration process itself, testing the predictive nature of the simulation. Typical device characteristics used for predictive testing includes threshold voltage versus gate length measurements for a non-zero substrate bias.

7.8.2: Tuning Oxidation Parameters

During oxidation, interstitials are injected into the silicon substrate by the advancing interface. The first parameter to tune is the fraction of consumed silicon atoms that are re-injected back into the substrate as interstitials. In ATHENA, the related tuning parameter is called THETA.0 and is defined in the INTERSTITIAL statement. THETA.0 has been found to be slightly different for wet and dry oxides. The default value is reasonably accurate for dry oxides but some tuning may be required for wet oxidation.

The major effect of interstitial injection during gate oxidation is to create enhanced diffusion of the threshold adjust implant. The measured threshold voltage of the final device is very sensitive to the dopant concentration near the silicon-gate oxide interface. Consequently, threshold voltage measurements are a sensitive indicator of interstitial behavior. Oxidation, however, is not the only source of interstitial injection. The source-drain and LDD implants also induce a large concentration of interstitials. In order to isolate oxidation enhanced diffusion, the threshold voltage of a long gate length device is used, preferably where L=20 µm or more, so that the threshold voltage will be little influenced by damage near the source-drain regions.

Interstitials injected by source-drain implant damage can travel up to 10 µm along the surface before recombination takes place. A gate length of 20 µm is recommended as the minimum gate length for calibration so this can allow the interstitials to diffuse 10 µm along the surface from both the source and drain ends without effecting diffusion near the center of the device. In summary, tuning THETA.0 involves the comparison of modeled and measured threshold voltage data for a long gate-length device.