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SRAM uses 6-Transistor to store a bit. SRAM is dominant form of embedded memory. It comprises 60- 70% chip area and 75% - 85% transistor count. As the logic gates density is increasing correspondingly the memory density must increase.

Statistical dopent fluctuations, variation in oxide thickness and line edge roughness increases the spread in V Th and I ON /I OFF in nano-scale regime [Murari 2003]. Increased leakage and parametric variations are making scaling of 6-T SRAM memory array difficult.

Due to fundamental physical limit to scaling, the era of conventional linear scaling of transistor dimensions has ended. Power dissipation and process induced variations have become the major issues for continued scaling of Si MOSFETs in future generation.

New materials and device structure are needed to continue the scaling trend as seen in ITRS-2003 Road map given in Figure 2.23.

According to ITRS 2003, by 2014 L Gate = 35nm, V DD = 0.4V and clock frequency = 30GHz.

Shrinking geometries, low power voltages and high frequency have a negative impact on

reliability. These enhanced features have increased the failure rates. New and innovative methods to meet the challenges of nano miniaturization.

Multiple core with threading has been one innovation for solving the thermal management at nano level.

Copper interconnect provides higher electromagnetic threshold than Aluminum. So Industry is adopting Cu interconnects.

Fault avoidance and fault tolerance are the possible ways of improved reliability.

Fault avoidance relies on improved materials, improved manufacturing processes and improved circuit design. Cu interconnects is an example of improved materials.

SOI (Silicon-on-Insulator) is the process solution for lower circuit sensitivity to particle induced transients. Fault tolerance is implemented at circuit and system level. It relies on error detection and error correction code.

  1. Future Generation Integrated Circuits.

Human appetite for computation has grown faster than the processors power of real life computers. We need more powerful processors just to keep up with modern applications like interactive multi-media, mobile computing and wireless communication. In addition battery power is at premium in mobile computing environment hence power aware components/systems are indispensible.

Low power design can be achieved at different level of the system- basic process/device level (threshold reduction, multi-threshold deices), at circuit level (transistor sizing, logic optimization, activity driven power down, low swing logic, adiabatic switching), at architecture level (voltage scaling, parallelism,, instruction set , signal correlation) at algorithm level( complexity, concurrency, locality, regularity, data representation) and at system level.(design partitioning and power down).

We have to simultaneously look at performance-power-cost product . This will lead to new computer architecture.

As we scale down the dimensions for each new generation technology, new areas of applications are emerging.

To continue its historical growth and continue to follow Moore’s Law, the Semiconductor Industry will require advances at all fronts- from front end processors and lithography to design innovations, high performance process architecture and SOC solutions.

Further down the scaling strategy we are bound to hit a road block.

The recent development in the field of Graphene Transistors show that these could be a promising candidate for taking over the mantle for continued scaling down according to Moore’s Law.[Kreupl, Franz “ Carbon nano-tubes finally deliver”, Nature, . 484 , 321-322, 19 th April 2012; Franklin, Aaron D.;Luisier, Mathieu; Han, Shu-Jen;et.al. “Sub-10nm Carbon Nano tube Transistors”, Nano Letters Nature, 12, 758-762 (2012) ].

The present Graphene Transistor using single walled Carbon nano-tube(SWCNT) of 9nm at a supply voltage of 0.4V switches from ‘0’ to ‘1’. The current ratio of ON to OFF is 10,000 times which is excellent for LOGIC applications.. This operates at low voltage hence it mitigates the demand in energy. The only difficulty is in fabricating these devices because of non-availability of SWCNT of one flavor.

In contrast according to IRTS 2011[ITRS2011 Edition , Front End Processors, Go.nature.com/qykuh1(2011)], a similar sized Si MOSFET of 9nm gate length and operating at 0.64V will arrive in the market in 2022 and we cannot anticipate the cost.

So it is ripe time that we explore for alternatives if the present rate of miniaturization and development has to be maintained. The Future Generation Integrated Circuits is discussed in Chapter 8 of this Collectrion.

Questions & Answers

a perfect square v²+2v+_
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algebra 2 Inequalities:If equation 2 = 0 it is an open set?
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or infinite solutions?
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Kristine 2*2*2=8
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Differences Between Laspeyres and Paasche Indices
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J, combine like terms 7x-4y
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f(n)= 2n + 1
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. After 3 months on a diet, Lisa had lost 12% of her original weight. She lost 21 pounds. What was Lisa's original weight?
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preparation of nanomaterial
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Yes, Nanotechnology has a very fast field of applications and their is always something new to do with it...
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Prasenjit Reply
At high concentrations (>0.01 M), the relation between absorptivity coefficient and absorbance is no longer linear. This is due to the electrostatic interactions between the quantum dots in close proximity. If the concentration of the solution is high, another effect that is seen is the scattering of light from the large number of quantum dots. This assumption only works at low concentrations of the analyte. Presence of stray light.
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Source:  OpenStax, Solid state physics and devices-the harbinger of third wave of civilization. OpenStax CNX. Sep 15, 2014 Download for free at http://legacy.cnx.org/content/col11170/1.89
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