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PWM based Digital to Analog Conversion

PCM to Duty Cycle Conversion

The interrupt service routine

The process described in the previous section is executed in the Interrupt Service Routine (ISR). The ADC conversion is triggered by the ePWM block when the PWM period starts (every 102.4 msecs). The ADC generates an interrupt at the end of conversion. The interrupt service routine updates the PWM duty cycle (CMPA value) on the value of this sample. The new duty cycle will be loaded in the beginning of the next PWM period. The process is described in Figure 6.

Timing Diagram

Output stage:

This module contains the H-bridge, and a Low Pass Filter to remove high frequency components, leaving only the audio-frequency content. This module basically implements a Digital to Analog Converter using a PWM signal generator and a Low Pass Filter as shown in . This method is described in .

PWM based Digital to Analog Conversion

The basic configuration of a D-Class amplifier is the Half-Bridge (H-Bridge) configuration. Two output transistors operate as switches, driven by complementary PWM signals. One of the transistors is off (current through it is close zero), while the remaining one is on (voltage across it is close to zero), keeping the power dissipation very low.

H-Bridge Power Topology

The full-bridge Class D amplifier comprises two half bridges, driven by synchronized PWM signals, having two alternate conduction paths through the load, each one having a pair of transistor conducting while the remaining pair is off.

Output Stage Schematics

Implementation

This section will describe the process of building a Simulink model for code generation according to description in chapter .

In the first part the framework for interrupt handling will be created. The second section will describe the creation of the Interrupt Service Routine.

Interrupt

  1. The "F2808 eZDSP" block
  2. The "Hardware Interrupt" Block
    The Interrupt should be generated at the end of conversion of group A, (CPU Values=1 and PIE Values=1) as shown in Figure 12.
    The "Hardware Interrupt" Selection Table
  3. The Hardware Interrupt Configuration
  4. The "Function-Call Subsystem" Block
  5. You may also change colors, and name the blocks as shown here.
    The Class-D Amplifier Model

Pcm to pwm conversion

  1. The "ADC" Block
    The block should be configured to use channel 0 of module A, triggered by ePWMxA, and post an interrupt at the end of conversion as shown:
    The "ADC" Configuration
  2. The "ePWM" block
    The blocks should be configured as shown in the following figures:
    The "ePWM1" block Configuration
    The "ePWM2" block Configuration
  3. The "Shift Arithmetic" Block
    The "Shift Arithmetic" Block Configuration
  4. The Class D Amplifier Model

Running the model:

  1. The System
    Voltage Supply
  2. Build and run the model "CTRL-B".
  3. The amplifier should start working, connect your audio source, and enjoy the music.

Things to try

This example's objective was to show the use of the F2808 blocks, it is certainly not the best implementation, but it serves as the basis for additional features and enhancements like:

  • Use Oversampling
  • Use the High-Resolution PWM
  • Add Signal Processing (Filtering, Equalization, Gain Control) features to the amplifier

References

  1. "eZdspTM F2808 Technical Reference", Spectrum Digital, 2005 (External Link)
  2. David M. Alter, " Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x", TI Application Report SPRAA88 , September 2008 (External Link)

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