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Appendix III describes the next generation technologies being developed as Optical Lithography reaches its resolvable limit of minimum feature size of 30nm.

Appendix III

Five Alternatives of Next Generation Lithography

[“ Next Generation Lithography” by Eric J. Lerner, June 1999,American Institute of Physics,pp 18 to 21.]

In four decades following the invention of IC chip, speed has doubled every 3 years and smallest feature size has scaled down by 2 every 6 years in accordance with Moore’s Law. This accounts for half the increase in Instruction per second executed by a given Computer of a given technology. The other half of the increase in IPS(instruction per second) has come about by the improvement in the architecture of microprocessor chip. Von Neumann sequential architecture has evolved into parallel architecture such as pipelining, systolic and data flow architecture. This has enabled to carry out complex instruction in reduced number of machine cycles. With the downward scaling of the devices, the clock speed has increased and simultaneously the number of machine cycles utilized to carry out an instruction has decreased. Both these factors increase the computational speed of a given computer of a given technology.

As devices have been scaled down, the line width has decreased. This has required that the wavelength of the light used in the photo-lithography is correspondingly decreased according to the formula:

W = minimum feature size=(according to Rayleigh Equation)=k.λ/(NA)

where NA(numerical aperture)=n.Sin(α) = d/(2f);

n= index of refraction of the medium surrounding the lens and α = acceptance angle of the lens system;

d= aperture diameter and f = focal length.

k= resolution factor.

Lithography underlies the entire I.C. technology. I.C chips are created by alternatively etching the oxide layer and creating a window pattern, through the window pattern carrying out the diffusion of dopents or implanting the dopents. Etching out a window pattern involves a pattern of photo resist imprinted on the chip through Photo Lithography Technique. The photo-lithography involves masks. Masks consist of chromium lines laid on quartz substrate. They are generated by computer controlled electron beams which lay down the pattern of chromium lines. The masks are 4 times larger and wider than the circuit pattern actually required. By optical projection the mask pattern is reduced 4 times to the correct size. This enables the mask generation more accurate and technically viable. In the mask the minimum feature size is 4 times the actual size.

Below 30nm we have to go for Next Generation Lithography. The five alternatives are:

  1. Extreme Ultra-Violet Lithography;
  2. X-Ray Proximity Lithography;
  3. Projection Electron Beam Technology;
  4. Ion Projection Lithography;
  5. Improved Optical Lithography.
  1. Extreme Ultra-Violet Lithography(EUV lithography):

The equipment set-up has been described in Part 3 of the main text in Figure 3 . The description of the setup is as follows:

Laser produced plasma

↓ radiation

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Source:  OpenStax, Solid state physics and devices-the harbinger of third wave of civilization. OpenStax CNX. Sep 15, 2014 Download for free at http://legacy.cnx.org/content/col11170/1.89
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