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You will learn more assembly instructions in this lab.

Typical assembly operations

Loading constants to registers

Quite often you need to load a register with a constant. The C62x instructions you can use for this task are MVK , MVKL , and MVKH . Each of these instructions can load a 16-bit constant to a register. Read and understandthe description of these instructions in the manual.

(Loading constants): Write assembly instructions to do the following:

  • Load the 16-bit constant 0xff12 to A1 .
  • Load the 32-bit constant 0xabcd45ef to B0 .

Intentionally left blank.

Register moves, zeroing

Contents of one register can be copied to another register by using the MV instruction. There is also the ZERO instruction to set a register to zero. Learn how to use these instructions byreading the appropriate TI manual pages.

Loading from memory to registers

Because the C62x processor has the so-called load/store architecture, you must first load up the content of memoryto a register to be able to manipulate it. The basic assembly instructions you use for loading are LDB , LDH , and LDW for loading up 8-, 16-, and 32-bit data from memory. (There are some variations to theseinstructions for different handling of the signs of the loaded values.) Read and understand how these instructionswork.

However, to specify the address of the memory location to load from, you need to load up another register (used as anaddress index) and you can use various addressing modes to specify the memory locations in many different ways. The addressing modes is the method by which aninstruction calculates the location of an object in memory. The table below lists all the possible different ways tohandle the address pointers in C62x CPU. Note the similarity with the C pointer manipulation.

Syntax Memory address accessed Pointer modification
*R R None
*++R R Preincrement
*--R R Predecrement
*R++ R Postincrement
*R-- R Postdecrement
*+R[disp] R+disp None
*-R[disp] R+disp None
*++R[disp] R+disp Preincrement
*--R[disp] R+disp Predecrement
*R++[disp] R+disp Postincrement
*R--[disp] R+disp Postdecrement

The [disp] specifies the number of elements in word, halfword, or byte, depending on theinstruction type and it can be either 5-bit constant or a register . The increment/decrement of the index registers are also in termsof the number of bytes in word, halfword or byte. The addressing modes with displacements are useful when a blockof memory locations is accessed. Those with automatic increment/decrement are useful when a block is accessedconsecutively to implement a buffer, for example, to store signal samples to implement a digital filter.

(Load from memory): Assume the following values are stored in memory addresses:

100h fe54 7834h 104h 3459 f34dh108h 2ef5 7ee4h 10ch 2345 6789h110h ffff eeddh 114h 3456 787eh118h 3f4d 7ab3h

Suppose A10 = 0000 0108h . Find the contents of A1 and A10 after executing the each of the following instructions.

  • LDW .D1 *A10, A1
  • LDH .D1 *A10, A1
  • LDB .D1 *A10, A1
  • LDW .D1 *-A10[1], A1
  • LDW .D1 *+A10[1], A1
  • LDW .D1 *+A10[2], A1
  • LDB .D1 *+A10[2], A1
  • LDW .D1 *++A10[1], A1
  • LDW .D1 *--A10[1], A1
  • LDB .D1 *++A10[1], A1
  • LDB .D1 *--A10[1], A1
  • LDW .D1 *A10++[1], A1
  • LDW .D1 *A10--[1], A1

Intentionally left blank.

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Source:  OpenStax, Finite impulse response. OpenStax CNX. Feb 16, 2004 Download for free at http://cnx.org/content/col10226/1.1
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