0.14 Mix’n’match receiver design  (Page 7/9)

Tuning and testing

The testing and verification stage of receiver design is not a simple matter because there are so many thingsthat can go wrong. (There is so much stuff that can happen!) Of course, it is always possible to simply build a prototypeand then test to see if the specifications are met. Such a haphazard approach may result in a workingreceiver, but then again, it may not. Surely there is a better way! This section suggests a commonsense approach that is not uncommonamong practicing engineers. It represents a “practical” compromise between excessive analysis(such as one might find in some advanced communication texts) and excessive trial and error (such as“try something and cross your fingers”).

The idea is to construct a simulator that can create a variety of test signals that fall within the ${\mathcal{M}}^6$ specification. The parameters within the simulator can thenbe changed one at a time, and their effect noted on various candidate receivers. By systematically varying thetest signals, the worst components of the receiver can beidentified and then replaced. As the tests proceed, the receiver gradually improves.As long as the complete set of test signals accurately represents the range of situations that will be encounteredin operation, the testing will lead to a successful design.

Given the particular stage one and two design choices for the ${\mathcal{M}}^6$ receiver, the previous section outlined the factors that may degrade the performance of the receiver.The following steps suggest some detailed tests that may facilitate the design process:

• Step 1: Tuning the Carrier Recovery As shown in Chapter  [link] , any of the carrier recovery algorithms are capable of locatinga fixed phase offset in a receiver in which everything else is operating optimally.Even when there is noise or ISI, the best settings for the frequency and phase of the demodulationsinusoid are those that match the frequency and phase of the carrier of the IF signal.For the ${\mathcal{M}}^6$ receiver, there are two issues that must be considered.First, the ${\mathcal{M}}^6$ specification allows the frequency to be (somewhat) different from its nominal value.Is a dual-loop structure needed? Or can a single loop adequately track the expected variations?Second, the transmitter phase may be jittering. The user choosable features of thecarrier recovery algorithms are the LPF and the algorithm stepsize, both of which influencethe speed at which the estimates can change. Since the carrier recovery scheme needs to track a time-varyingphase, the stepsize cannot be chosen too small. Since a large stepsize increases the error dueto phase jitter, it cannot be chosen too large. Thus, an acceptable stepsize will represent a compromise.To conduct a test to determine the stepsize (and LPF) requires creating test signals that have a variety ofoff-nominal frequency offsets and phase jitters. A simple way to model phase jitter is to add alowpass filtered version of zero-mean white noise to a nominal value.The quality of a particular set of parameters can then be measured by averaging (over all the test signals)the mean squared recovery error. Choosing the LPF and stepsize parameters to make this error as smallas possible gives the “best” values. This average error provides a measure of theportion of the total error that is due to the carrier recovery component in the receiver.
• Step 2: Tuning the Timing Recovery As shown in Chapter  [link] , there are several algorithms that can be used to find the best timing instantsin the ideal setting. When the channel impairment consists purelyof additive noise, the optimal sampling times remain unchanged, though the estimates will likely be more noisy.As shown by Example  [link] , and in [link] , however, when the channel contains ISI, the answer returnedby the algorithms differs from what might be naively expected. There are two parts to the experiments at this step.The first is to locate the best timing recovery parameter for each test signal. (This value will be needed in thenext step to assess the performance of the equalizer.) The second part is to find the mean squared recovery errordue to jitter of the timing recovery algorithm. The first part is easy. For each test signal, run thechosen timing recovery algorithm until it converges. The convergent value gives the timing offset(and indirectly specifies the ISI) to which the equalizer will need to respond. (If it jiggles excessively,then decrease the stepsize.) Assessing the mean squared recovery error due to timingjitter can be done much like the measurement of jitter for the carrier recovery: measure the average errorthat occurs over each test signal when the algorithm is initialized at its optimum answer; then average overall the test signals. The answer may be affected by the various parameters of the algorithm: the $\delta$ that determines the approximation to the derivative, the l parameter that specifies the time support of the interpolation, and the stepsize (these variable namesare from the first part of the timing recovery algorithm clockrecDD.m .) In operation, there may also be slight inaccuracies in thespecification of the clock period. When the clock period at the transmitter and receiver differ,the stepsize must be large enough so that the timing estimates can followthe changing period. (Recall the discussion surrounding Example  [link] .) Thus, again, there is a tension between a large stepsizeneeded to track rapid changes and a small stepsize to minimize the effect of the jitter onthe mean squared recovery error. In a more complex environment, in which clock phases might bevarying, it might be necessary to follow a procedure more like that considered in step 1.
• Step 3: Tuning the Equalizer After choosing the equalizer method (as specified by the performance function), there are a number of parameters that must be chosenand decisions that must be made in order to implement the linear equalizer. These are
  • the order of the equalizer (number of taps),
  • the initial values of the equalizer,
  • the training signal delay (if using the training signal), and
  • the stepsize.
  As in the previous steps, it is a good idea to create a collection of test signals using a simulation of the transmitter.To test the performance of the equalizer, the test signals should contain a variety of ISI channels and/or additive interferences.As suggested in Chapter  [link] , in a high SNR scenario the $T$ -spaced equalizer tries to implement an approximation of the inverse of the ISI channel.If the channel is mild, with all its roots well away from the unit circle, then its inverse may be fairly short.But if the channel has zeros that are near the unit circle, then its FIR inverse may need to be quite long.While much can be said about this, a conservative guideline is that the equalizer should befrom two to five times longer than the maximum anticipated channel delay spread.One subtlety that arises in making this decision and in consequent testing is that any channel ISI that is added intoa simulation may appear differently at the receiver because of the sampling. This effect was discussed at lengthin [link] , where it was shown how the effective digital model of the channel includes thetiming offset. Thus (as mentioned in the previous step) assessing the “actual” channel to which the equalizer willadapt requires knowing the timing offset that will be found by the timing recovery. Fortunately, in the ${\mathcal{M}}^6$ receiver structure of [link] , the timing recovery algorithm operates independently of theequalizer, and so the optimal value can be assessed beforehand.For most of the adaptive equalizers in Chapter  [link] , the center spike initialization is used. This was justifiedin [link] as a useful method of initialization. Only if there is some concrete a prior knowledge of the channel characteristicswould other initializations be used. The problem of finding an appropriate delay was discussedin [link] , where the least squares solution was recomputed for each possible delay.The delay with the smallest error was the best. In a real receiver, it will not be possible to do anextensive search, and so it is necessary to pick some delay. The ${\mathcal{M}}^6$ receiver uses correlation to locate the marker sequence and this can be used to locate thetime index corresponding to the first training symbol. This location plus half the length of the equalizershould correspond closely to the desired delay. Of course, this value may change depending on theparticular ISI (and channel lengths) used in a given test signal. Choose a value that, over the completeset of test signals, provides a reasonable answer. The remaining designer-selected variable is stepsize.As with all adaptive methods, there is a tradeoff inherent in stepsize selection:making it too large can result in excessive jitter or algorithm instability, whilemaking it too small can lead to an unacceptably long convergence time.A common technique is to select the largest stepsize consistent with achievement of thecomponent's assigned asymptotic performance threshold.
• Step 4: Frame Synchronization Any error in locating the first symbol of each four-symbol block can completely garble the reconstructed text.The frame synchronizer operates on the output of the quantizer, which should contain few errors once the equalizer, timing recovery,and phase recovery have converged. The success of frame synchronization relies on thepeakiness of the correlation of the marker/training sequence. The chosen marker/training sequence “A0Oh well whatever Nevermind”should be long enough that there are few false spikes when correlating tofind the start of the message within each block. To test software written to locate the marker, feed it a samplesymbol string assembled according to the specifications described in the previous section as if the downconverter,clock timing, equalizer, and quantizer had recovered the transmitted symbol sequence perfectly.