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Using the DMA controller included in the MSP-EXP430FG4618 Development Tool transfer a sinusoidal wave to the DAC12_0's output. Timer_A operates in upmode with TACCR1 loading DAC12_0 on rising edge and DAC12_0IFG triggering next DMA1 transfer. DAC12_0 uses internal 1.5V reference.

Laboratory dma: lab2 - sinusoidal waveform generator

Introduction

This laboratory gives an example of the use of the DMA peripheral available in the MSP-EXP430FG4618 Development Tool. It requires the configuration of the DMA Source and Destination Addresses Registers, DMA Size Address Register; DMA Control Registers, DMA Channel 0 Control Register, DAC12 control register and Timer_A control register in order to generate a sinusoidal waveform.

Overview

This laboratory ( Lab2_DMA.c ) uses the DMA controller to automatically transfer data between data memory and the DAC12 data register. A sinusoidal waveform is produced at the output of the DAC, without CPU intervention.

Resources

This laboratory uses the following peripherals:

- DMA controller;

- DAC;

- ADC (reference generator: V REF+ );

- Timer_A;

- Low power mode.

Software application organization

The successive samples needed to produce the sinusoidal waveform using the DAC are stored in the data vector Sin_tab , which contains 32 points:

//--------------------------------------------------------- // 12-bit Sine Lookup table with 32 steps//--------------------------------------------------------- int Sin_tab[32]= {2048, 2447, 2831, 3185, 3495, 3750, 3939, 4056, 4095, 4056, 3939, 3750, 3495, 3185, 2831, 2447,2048, 1648, 1264, 910, 600, 345, 156, 39, 0, 39, 156, 345, 600, 910, 1264, 1648};

The software begins by disabling the watchdog timer, followed by activating the internal reference voltage V REF+ . The source and destination registers of the data vector to be transferred by the DMA channel are loaded into the data vector Sin_tab (source) address and with the DAC12 data register (destination) address. There are 32 data values to be transferred.

The data transfer is initiated whenever the DAC12IFG flag is enabled. In this application, the DAC interrupt should be disabled.

The DMA controller is configured to operate in repeat mode, to transfer a word whenever the previous event occurs. The data source address is set to increment after each transfer, while the destination address must remain constant.

The timer is set to generate the PWM signal through the capture/compare unit TACCR1. SMCLK is the clock signal that counts up to the value in the TACCR0 register.

Finally, the settings and interrupts are enabled and the device enters into low power mode LPM0.

System configuration

Dac12 reference voltage activation

The DAC12 requires a reference voltage. One of the options is to use the internal voltage V REF+ . Set the ADC12CTLO register to activate this voltage:

ADC12CTL0 = REFON; // Internal reference

Dma controller configuration:

Configure the registers DMA0SA (source), DMA0DA (destination) and DMA0SZ (size) to transfer 32 words between the source vector Sin_tab and the DAC12_0DAT data destination register:

DMA0SA = (void (*)( ))&Sin_tab; // Source block addressDMA0DA = (void (*)( ))&DAC12_0DAT; // Destination single addressDMA0SZ = 0x20; // Block size

Configure the register DMACTL0 to provide a data transfer whenever the DAC12IFG flag is set:

DMACTL0 = DMA0TSEL_5; // DAC12IFG trigger

Configure the register DMA0CTL to carry out a repeated simple data transfer, increasing the data source address:

DMA0CTL = DMADT_4 | DMASRCINCR_3 | DMAEN; // Repeated single transfer,// DMA source address increment, // since DMASRCBYTE = 0, the source address increments by// two (word-word)

Setup dac12

The DAC12 will update its output whenever there is the activation of the signal TA1. The DAC full-scale should be 1x reference voltage. Choose a medium relationship between the DAC’s current and average conversion speed:

DAC12_0CTL = DAC12LSEL_2 | DAC12IR | DAC12AMP_5 | DAC12IFG | DAC12ENC; // Rising edge of Timer_A.OUT1 (TA1),// DAC12 full-scale output: 1x reference voltage, // Input and output buffers: Medium freq./current,// Enable DAC12

Timer_a configuration

Timer_A is responsible for synchronizing data transfers between memory and the DAC12. The Timer_A input receives as the SMCLK signal (1.048576 MHz) and must have a 30 msec counting period. What value needs to be written to TACCR0, in order to achieve this counting period:

TACCR0 = 32-1; // Clock period of TACCR0 TACTL = TASSEL_2 | MC_1; // SMCLK, continuous mode

The capture/compare unit TACCR1 should generate a PWM signal in set/reset mode. Configure the unit appropriately:

TACCTL1 = OUTMOD_3; // TACCR1 set/reset TACCR1 = 20; // TACCR1 PWM Duty Cycle

Analysis of operation

The verification of this laboratory is achieved by using an oscilloscope probe to monitor the output of the DAC12 Channel 0, available on header 8 pin 6.

This example and many others are available on the MSP430 Teaching ROM.

Request this ROM, and our other Teaching Materials here (External Link)

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Source:  OpenStax, Teaching and classroom laboratories based on the “ez430” and "experimenter's board" msp430 microcontroller platforms and code composer essentials. OpenStax CNX. May 19, 2009 Download for free at http://cnx.org/content/col10706/1.3
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