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The single operand instruction is formatted as follows:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opcode | B/W | Ad | D/S-Reg |
| Bit | Description | |
| 15-7 | opcode | |
| 6 | B/W | Byte or word operation:B/W=0: word operation; B/W=1: byte operation |
| 5-4 | Ad | The addressing bits responsible for the addressing mode used for the source operand (src) |
| 3-0 | D/S-Reg | The working register used for the destination operand (dst) or for the source operand (src) |
The next table shows the single operand instructions that are not emulated.
| Mnemonic | Operation | Description |
| Logical and register control instructions | ||
| RRA(.B or .W) dst | MSB→MSB→…LSB→C | Roll destination right |
| RRC(.B or .W) dst | C→MSB→…LSB→C | Roll destination right through (from) carry |
| SWPB(.B or .W) dst | Swap bytes | Swap bytes in destination |
| SXT dst | bit 7→bit 8…bit 15 | Sign extend destination |
| PUSH(.B or .W) src | SP-2→SP, src→@SP | Push source to stack |
| Program flow control instructions | ||
| CALL(.B or .W) dst | SP-2→SP, PC+2→@SPdst→PC | Subroutine call to destination |
| RETI | TOS→SR, SP+2→SPTOS→PC, SP+2→SP | Return from interrupt |
Conditions for status bits, depending on the single operand instruction result.
| Status bits | ||||
| Mnemonic | V | N | Z | C |
| Logical and register control instructions | ||||
| RRA(.B or .W) dst | =0 | =1, negative result=0, otherwise | =1, null result,=0, otherwise | Loaded from LSB |
| RRC(.B or .W) dst | =1, dst positive&C=1=0, otherwise | =1, negative result=0, otherwise | =1, null result,=0, otherwise | Loaded from LSB |
| SWPB(.B or .W) dst | - | - | - | - |
| SXT dst | =0 | =1, negative result=0, otherwise | =1, null result,=0, otherwise | =1, not zero=0, otherwise |
| PUSH(.B or .W) src | - | - | - | - |
| Data instructions | ||||
| CALL(.B or .W) dst | - | - | -- | - |
| RETI | restored from stack | restored from stack | restored from stack | restored from stack |
The jump instruction is formatted as follows:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opcode | C | 10 bit PC offset |
| Bit | Description | |
| 15-13 | opcode | |
| 12-10 | C | |
| 9-0 | PC offset | PCnew = PCold + 2 + PCoffset × 2 |
The following table shows the program flow control (jump) instructions that are not emulated.
| Mnemonic | Description |
| Program flow control instructions | |
| JEQ/JZ label | Jump to label if zero flag is set |
| JNE/JNZ label | Jump to label if zero flag is reset |
| JC label | Jump to label if carry flag is set |
| JNC label | Jump to label if carry flag is reset |
| JN label | Jump to label if negative flag is set |
| JGE label | Jump to label if greater than or equal |
| JL label | Jump to label if less than |
| JMP label | Jump to label unconditionally |
The next gives the different emulated instructions. This table also contains the type of operation and the emulated instruction based on the core instructions.
| Mnemonic | Operation | Emulation | Description |
| Arithmetic instructions | |||
| ADC(.B or .W) dst | dst+C→dst | ADDC(.B or .W) #0,dst | Add carry to destination |
| DADC(.B or .W) dst | dst+C→dst (decimally) | DADD(.B or .W) #0,dst | Decimal add carry to destination |
| DEC(.B or .W) dst | dst-1→dst | SUB(.B or .W) #1,dst | Decrement destination |
| DECD(.B or .W) dst | dst-2→dst | SUB(.B or .W) #2,dst | Decrement destination twice |
| INC(.B or .W) dst | dst+1→dst | ADD(.B or .W) #1,dst | Increment destination |
| INCD(.B or .W) dst | dst+2→dst | ADD(.B or .W) #2,dst | Increment destination twice |
| SBC(.B or .W) dst | dst+0FFFFh+C→dstdst+0FFh→dst | SUBC(.B or .W) #0,dst | Subtract source and borrow /.NOT. carry from dest. |
| Logical and register control instructions | |||
| INV(.B or .W) dst | .NOT.dst→dst | XOR(.B or .W) #0(FF)FFh,dst | Invert bits in destination |
| RLA(.B or .W) dst | CMSBMSB-1…LSB+1LSB0 | ADD(.B or .W) dst,dst | Rotate left arithmetically |
| RLC(.B or .W) dst | CMSBMSB-1…LSB+1LSBC | ADDC(.B or .W) dst,dst | Rotate left through carry |
| Data instructions | |||
| CLR(.B or .W) dst | 0→dst | MOV(.B or .W) #0,dst | Clear destination |
| CLRC | 0→C | BIC #1,SR | Clear carry flag |
| CLRN | 0→N | BIC #4,SR | Clear negative flag |
| CLRZ | 0→Z | BIC #2,SR | Clear zero flag |
| POP(.B or .W) dst | @SP→tempSP+2→SPtemp→dst | MOV(.B or .W) @SP+,dst | Pop byte/word from stack to destination |
| SETC | 1→C | BIS #1,SR | Set carry flag |
| SETN | 1→N | BIS #4,SR | Set negative flag |
| SETZ | 1→Z | BIS #2,SR | Set zero flag |
| TST(.B or .W) dst | dst + 0FFFFh + 1dst + 0FFh + 1 | CMP(.B or .W) #0,dst | Test destination |
| Program flow control | |||
| BR dst | dst→PC | MOV dst,PC | Branch to destination |
| DINT | 0→GIE | BIC #8,SR | Disable (general) interrupts |
| EINT | 1→GIE | BIS #8,SR | Enable (general) interrupts |
| NOP | None | MOV #0,R3 | No operation |
| RET | @SP→PCSP+2→SP | MOV @SP+,PC | Return from subroutine |
Conditions for status bits, depending on the emulated instruction result.
| Status bits | ||||
| Mnemonic | V | N | Z | C |
| Arithmetic instructions | ||||
| ADC(.B or .W) dst | =1, Arithmetic overflow=0, otherwise | =1, negative result=0, if positive | =1, null result=0, otherwise | =1, dst from 0FFFFh to 0000=0, otherwise |
| DADC(.B or .W) dst | - | =1, MSB=1=0, otherwise | =1, dst=0=0, otherwise | =1, dst from 99(99) to 00(00)=0, otherwise |
| DEC(.B or .W) dst | =1, Arithmetic overflow=0, otherwise | =1, negative result=0, if positive | =1, dst contained 1=0, otherwise | =1, dst contained 0=0, otherwise |
| DECD(.B or .W) dst | =1, Arithmetic overflow=0, otherwise | =1, negative result=0, if positive | =1, dst contained 2=0, otherwise | =1, dst contained 0 or 1=0, otherwise |
| INC(.B or .W) dst | =1, dst contained 07(FF)h=0, otherwise | =1, negative result=0, if positive | =1, dst contained FF(FF)h=0, otherwise | =1, dst contained FF(FF)h=0, otherwise |
| INCD(.B or .W) dst | =1, dst contained 07(FFE)h=0, otherwise | =1, negative result=0, if positive | =1, dst contained FF(FE)h=0, otherwise | =1, dst contained FF(FF)h or FF(FE)h=0, otherwise |
| SBC(.B or .W) dst | =1, Arithmetic overflow=0, otherwise | =1, negative result=0, if positive | =1, null result,=0, otherwise | =1, if no borrow=0, otherwise |
| Logical and register control instructions | ||||
| INV(.B or .W) dst | =1, negative initial dst=0, otherwise | =1, negative result=0, if positive | =1, dst contained FF(FF)h=0, otherwise | =1, not zero=0, otherwise |
| RLA(.B or .W) dst | =1, Arithmetic overflow=0, otherwise | =1, negative result=0, if positive | =1, null result,=0, otherwise | Loaded from MSB |
| RLC(.B or .W) dst | =1, Arithmetic overflow=0, otherwise | =1, negative result=0, if positive | =1, null result,=0, otherwise | Loaded from MSB |
| Data instructions | ||||
| CLR(.B or .W) dst | - | - | - | - |
| CLRC | - | - | - | =0 |
| CLRN | - | =0 | - | - |
| CLRZ | - | - | =0 | - |
| POP(.B or .W) dst | - | - | - | - |
| SETC | - | - | - | =1 |
| SETN | - | =1 | - | - |
| SETZ | - | - | =1 | - |
| TST(.B or .W) dst | =0 | =1, dst negative=0, otherwise | =1, dst contains zero=0, otherwise | =1 |
| Program flow control | ||||
| BR dst | - | - | - | - |
| DINT | - | - | - | - |
| EINT | - | - | - | - |
| NOP | - | - | - | - |
| RET | - | - | - | - |
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