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Instruction set
The MSP430 instruction set consists of 27 core instructions. Additionally, it supports 24 emulated instructions. The core instructions have unique op-codes decoded by the CPU, while the emulated ones need assemblers and compilers to generate their mnemonics.
There are three core-instruction formats:
- Double operand;
- Single operand;
- Program flow control - Jump.
Byte, word and address instructions are accessed using the .B, .W or .A extensions. If the extension is omitted, the instruction is interpreted as a word instruction.
The double operand instruction is formatted as follows:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opcode | S-Reg | Ad | B/W | As | D-Reg |
| Bit | Description | |
| 15-12 | opcode | |
| 11-8 | S-Reg | The working register used for the source operand (src) |
| 7 | Ad | The addressing bits responsible for the addressing mode used for the destination operand (dst) |
| 6 | B/W | Byte or word operation:B/W=0: word operation; B/W=1: byte operation |
| 5-4 | As | The addressing bits responsible for the addressing mode used for the source operand (src) |
| 3-0 | D-Reg | The working register used for the destination operand (dst) |
The next table shows the double operand instructions that are not emulated.
| Mnemonic | Operation | Description |
| Arithmetic instructions | ||
| ADD(.B or .W) src,dst | src+dst→dst | Add source to destination |
| ADDC(.B or .W) src,dst | src+dst+C→dst | Add source and carry to destination |
| DADD(.B or .W) src,dst | src+dst+C→dst (dec) | Decimal add source and carry to destination |
| SUB(.B or .W) src,dst | dst+.not.src+1→dst | Subtract source from destination |
| SUBC(.B or .W) src,dst | dst+.not.src+C→dst | Subtract source and not carry from destination |
| Logical and register control instructions | ||
| AND(.B or .W) src,dst | src.and.dst→dst | AND source with destination |
| BIC(.B or .W) src,dst | .not.src.and.dst→dst | Clear bits in destination |
| BIS(.B or .W) src,dst | src.or.dst→dst | Set bits in destination |
| BIT(.B or .W) src,dst | src.and.dst | Test bits in destination |
| XOR(.B or .W) src,dst | src.xor.dst→dst | XOR source with destination |
| Data instructions | ||
| CMP(.B or .W) src,dst | dst-src | Compare source to destination |
| MOV(.B or .W) src,dst | src→dst | Move source to destination |
Depending on the double operand instruction result, the status bits may be affected. The following gives the conditions for setting and resetting the status bits.
| Status bits | ||||
| Mnemonic | V | N | Z | C |
| Arithmetic instructions | ||||
| ADD(.B or .W) src,dst | =1, Arithmetic overflow=0, otherwise | =1, negative result=0, if positive | =1, null result=0, otherwise | =1, carry from result=0, if not |
| ADDC(.B or .W) src,dst | =1, Arithmetic overflow=0, otherwise | =1, negative result=0, if positive | =1, null result=0, otherwise | =1, carry from MSB result=0, if not |
| DADD(.B or .W) src,dst | - | =1, MSB=1=0, otherwise | =1, null result=0, otherwise | =1, result>99(99) |
| SUB(.B or .W) src,dst | =1, Arithmetic overflow=0, otherwise | =1, negative result=0, if positive | =1, null result=0, otherwise | =1, if no borrow=0, otherwise |
| SUBC(.B or .W) src,dst | =1, Arithmetic overflow=0, otherwise | =1, negative result=0, if positive | =1, null result=0, otherwise | =1, if no borrow=0, otherwise |
| Logical and register control instructions | ||||
| AND(.B or .W) src,dst | =0 | =1, MSB result set=0, if not set | =1, null result=0, otherwise | =1, not zero=0, otherwise |
| BIC(.B or .W) src,dst | - | - | - | - |
| BIS(.B or .W) src,dst | - | - | - | - |
| BIT(.B or .W) src,dst | =0 | =1, MSB result set=0, otherwise | =1, null result=0, otherwise | =1, not zero=0, otherwise |
| XOR(.B or .W) src,dst | =1, both operands negative | =1, MSB result set=0, otherwise | =1, null result,=0, otherwise | =1, not zero=0, otherwise |
| Data instructions | ||||
| CMP(.B or .W) src,dst | =1, Arithmetic overflow=0, otherwise | =1, src>=dst=0, src<dst | =1, src=dst=0, otherwise | =1, carry from MSB result=0, if not |
| MOV(.B or .W) src,dst | - | - | - | - |
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