3.2 Review question: memory management  (Page 4/4)

      2    0          60        161      0          1

      1    1          130      160      1          0

      0    2          26        162      1          0

      3    3          20        163      1          1

      A page fault to virtual page 4 has occured at time 164. Which page frame will have its contents replaced for each of the following memory management policies? Explain why in each case.

a.       FIFO (first-in-first-out)

            Frame 3 since it was loaded the longest ago at time 20.

b.      LRU (least recently used)

            Frame 1 since it was referenced the longest ago at time 160.

c.       Clock

            Clear R in Frame 3 (oldest loaded), clear R in Frame 2 (next oldest loaded), victim Frame is 0 since R=0.

d.      Optimal (Use the following reference string.)

            Replace the page in Frame 3 since the virtual page number 3 (in Frame 3) is used furthest in the future.

e.       Given the aforementioned state of memory just before the page fault, consider the following virtual page reference string: 4,0,0,0,2,4,2,1,0,3,2. How many page faults would occur if the working set policy with LRU were used with a window size of 4 instead of a fixed allocation? Show clearly where each fault would occur.

            There are 6 faults, indicated by *:

            (Window) - {working set}

            -----------------------

            (1 2 0 3) - {2 1 0 3}

            (2 0 3 4) - {2 0 3 4}*

            (0 3 4 0) - {0 3 4}

            (3 4 0 0) - {0 3 4}

            (4 0 0 0) - {0 4}

            (0 0 0 2) - {0 2}*

            (0 0 2 4) - {0 2 4}*

            (0 2 4 2) - {0 2 4}

            (2 4 2 1) - {2 4 1}*

            (4 2 1 0) - {2 4 1 0}*

            (2 1 0 3) - {2 1 0 3}*

            (1 0 3 2) - {2 1 0 3}

Consider a system with memory mapping done on a page basis and usin ga single-level page table. assume that hte necessary page table is always in memory.

a.       If a memory reference takes 200 ns, how long does a paged memory reference take?

400 nanoseconds. 200 to get the page table entry, and 200 to access the memory location

.

b.      Now we add an MMU that imposes an overhead of 20 ns on a hit or a miss. If we assume that 85% of all memory references hit in the MMU TLB, what is the Effective Memory Access Time (EMAT)?

There are two cases. First, when the TLB contains the entry required, we have 20 ns overhead on top of the 200 ns memory access time. Second, when the TLB does not contain the item, we have an additional 200 ns to get the required entry into the TLB:

            (220 * 0.85) + (420 * 0.15) = 250 ns

c.       Explain how the TLB hit rate affects the EMAT.

The higher the TLB hit rate is, the smaller the EMAT is, because the additional 200 ns penalty to get the entry into the TLB contributes less to the EMAT.

Assume that a task is divided into four equal-sized segments and that the system builds an eight-entry page descriptor table for each segment. thus, the system has a combination of segmentation and paging. assume also that the page size is 2 kbytes.

a.       What is the maximum size of each segment?

            (8 entries in the page table) x 2K = 16K.

b.      What is the maximum logical address space for the task?

            (16 K) x 4 segments per task = 64K.

c.       Assume that an element in physical location 00021ABC is accessed by this task. What is the format of the logical address that the task generates for it? What is the maximum physical address space for the system?

We know the offset is 11 bits since the page size is 2K. The page table for each segment has eight entries, so it needs 3 bits. That leaves 2 bits for the segment number. So the format of the address is 2 bits for segment number, 3 bits for page number, and 11 bits for offset.

 The physical address is 32 bits wide total, so the frame number must be 21 bits wide. Thus 00021ABC is represented in binary as:

            Frame                           Offset

            0000 0000 0000 0010 0001 1 | 010 1011 1100

            The maximum physical address space is 232 = 4 GB.

 Note that the virtual address space is only 16 bits wide: 11 for the offset, 3 for the page number, and 2 for the segment number. This means a process cannot logically address the entire 4GB space ... it is limited to only 64K.

Assume that we have a demand-paged memory with the page table held in registers. it takes 8 milliseconds to service a page fault if an empty frame is available or if the replaced page is not modified, and 20 milliseconds if the replaced page is modified. assume the page to be replaced is modified 70 percent of the time. memory access time is 100 nanoseconds.

      What is the maximum acceptable page-fault rate if we want the system to have an effective memory access time of 200 nanoseconds?

      EMAT = 200ns = X(100ns) + (1-X)(.70(20ms + 100ns) + .3(8ms + 100ns))

           = 100X + (1-X)(16.4ms)

           = 100X - 16,400,000X + 16,400,000

      X = 16399800/163999000

        = .9999939024

      Therefore the maximum acceptable page-fault rate is (1-X) = .00061%.